library library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity set_hour is
    port(add10: in std_logic;
        add1: in std_logic;
        qout_hour:out std_logic_vector(7 downto 0));
end;

architecture art of set_hour is

signal time10: std_logic_vector(3 downto 0);
signal time1: std_logic_vector(3 downto 0);
signal temp_out: std_logic_vector(7 downto 0);

begin
    p1:process(add10)
    begin
        if(temp10=2) then
            temp10<=0;
        else
            temp10<=temp10+1;
        end if;
        temp_out <= temp10 & temp1;
        qout_hour <= temp_out;
    end process;

    p2:process(add1)
    begin
        if(temp10=2 and temp1=3) then
            temp10=0;
            temp1=0;
        elsif(temp1=9) then
            temp10<=temp10+1;
            temp1=0;
        else
            temp1<=temp1+1;
        end if;
        temp_out <= temp10 & temp1;
        qout_hour <= temp_out;
    end process;
end art;

            